Chameleon > DevTalk

wrmsr/rdmsr on a per cpu/core basis

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valv:
Some machines are manufactured with TM1 completely disabled. In an attempt to activate it I didn't managed to attach each cpu and wrmsr to it (as TM1 needs to be enabled in that way: per cpu). All I could get is TM1 for the first cpu but next ones remain inaccessible.
Any knowledge on this, please ?

rocksteady:
Could it be that you're looking into Xeons valv?

I'm on the go right now, so can't check my documentation but IIRC, rdmsr & wrmsr must be executed @ priviledge level 0 or in real-address mode. Otherwise a #GP(0) spoils all the fun.

valv:
not only xeons.

Indeed, rdmsr & wrmsr should be executed in that way. But what am stuck at, is how to wrmsr to a cpu other than cpu0.
I need this to activate TM1 on each cpu. What I got so far is:

1) attempting to enable TM1 for all cpus:
* successfully enabled for cpu0
* cpu1 untouched/unchanged 2) attempting to enable TM2:
* ccessfully enabled for cpu0
* ccessfully enabled for cpu0That is no problem for TM2 as it is globally applied. But it is not the case of TM1.
Do u understand my problem now ?

anyway, thank u for replying :)

rocksteady:
Sorry valv i misread you, or rather it ringed a bell from a past project.

Are you investigating this for a broad array of CPUs/BIOSes ?

We've been looking into such options for Xeons some time ago when researching a project @work. One of my hw-eng guys was loosing hair over crippled implementations. A call to Intel revealed that different units will get you different surprises. I'm not sure how much of a pain it'll be to start investigating this for a broad range of CPUs and crappy BIOSes

Let me check if I can find something useful

valv:
thank u for caring.
some dell manufactured boards have tm1/tm2 or even both disabled (the case of hp hdx series).
what I found so far, is bit 21 (lock tm1) at 0x1aa. As of apple's definition, if this bit is set (when tm1 is enabled) a prochot# on one core would force tm1 on other cores. I don't know if tm1 has to be enabled on all cores and if is applicable to (say) core2/xeon...

any findings regarding the initial question and/or obscure msr/cpuid are welcome... for the sake of progress :)

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